claude-skills/pcb-ai-engineer/references/review_checklists.md

Review Checklists

1. Schematic Review Checklist

Walk through every item. Mark each as PASS / FAIL / N/A.

Power

• Every VDD/AVDD/VDDIO pin has a dedicated 100nF decoupling cap (placed close)
• Bulk capacitor (10µF+) present on each power rail at regulator output
• VDDA isolated with ferrite bead + dedicated caps (if MCU has analog supply)
• VCAP pin has capacitor per datasheet value (STM32 specific)
• All GND pins connected (including exposed thermal pad on QFN/DFN)
• Power sequencing considered for multi-rail designs
• Regulator input/output caps meet datasheet ESR requirements
• Input protection present (TVS, fuse, reverse polarity) if external power
• USB VBUS has resettable fuse (500mA for device, per USB spec)
• Battery circuit has undervoltage lockout if applicable

Reset & Boot

• NRST has 100nF cap to GND (RC filter for noise rejection)
• NRST has external pull-up (10kΩ typical) if not using reset IC
• BOOT0 pin pulled to defined state (typically GND via 10kΩ)
• BOOT1/other boot config pins at correct state for normal operation
• ESP32 EN pin: 10kΩ pull-up + 1µF cap (slow rise for reliable boot)
• ESP32 GPIO0: pull-up for normal boot, button to GND for programming

Clock

• Crystal load capacitors calculated from datasheet formula: CL = (C1 × C2) / (C1 + C2) + Cstray, where Cstray ≈ 3-5pF
• Crystal placed close to MCU oscillator pins (< 10mm trace length)
• Ground guard ring / pour around crystal area (EMI reduction)
• 32.768 kHz RTC crystal present if RTC needed (with its own load caps)

Signal Integrity

• USB D+/D- have ESD protection diodes (TPD2E001, PRTR5V0U2X, or similar)
• USB D+/D- traces are 90Ω differential impedance (controlled, matched length)
• I2C bus has external pull-up resistors (4.7kΩ default; 2.2kΩ for fast-mode+)
• SPI chip-select lines have pull-ups (prevent floating during boot)
• UART TX/RX: series resistor (22-100Ω) if crossing board boundaries
• High-speed signals (>10 MHz) have series termination resistors
• CAN bus: 120Ω termination resistor at each end of bus
• Analog inputs: RC low-pass filter if reading noisy signals

GPIO & Unused Pins

• No floating input pins (all unused GPIO tied high/low or set as output)
• LED current-limiting resistors present and correctly calculated
• Button/switch inputs have debounce circuit (RC or software)
• Test points on critical signals (power rails, I2C, SPI, UART)

Connectors

• Programming/debug header present (SWD for ARM, JTAG if needed)
• USB connector shield connected to GND (directly or via 1MΩ + 4.7nF)
• All connector pins assigned and documented
• Mechanical mounting holes present (M3 at corners, connected to GND or float)

2. DRC/ERC Checklist (pre-KiCad)

These should be verified in the Python code before generating KiCad files:

• Every Component has symbol, ref, and footprint defined
• No duplicate reference designators (R1, R1 conflict)
• Every net has at least two connections (no dangling nets)
• Power nets (VCC, GND) are explicitly named and consistent
• No unconnected component pins that should be connected
• Component values are specified where needed (resistors, capacitors)

Post-KiCad-generation (in KiCad ERC):

• Run ERC in KiCad schematic editor — zero errors
• Run DRC in KiCad PCB editor — zero errors
• Check for unconnected pads in PCB
• Verify copper pour connectivity (GND plane continuous)

3. BOM Review Checklist

• All components have manufacturer part number (MPN) or generic value
• All components have valid KiCad footprint assigned
• No DNP (Do Not Place) components without documented reason
• Passive component values are standard E-series (E12/E24/E96)
• Capacitor dielectric specified (X7R/X5R for decoupling, C0G for precision)
• Capacitor voltage rating ≥ 2× operating voltage (derating)
• Resistor power rating adequate for application
• Check JLCPCB basic parts availability (cost optimization)
• Second-source alternatives identified for critical components
• Total unique part count minimized (fewer unique values = cheaper assembly)

4. Manufacturing Review (pre-Gerber)

• Board outline defined with correct dimensions
• Minimum trace width / spacing meets fab capability (typically 0.15mm/0.15mm)
• Via size meets fab capability (typically 0.3mm drill, 0.6mm annular ring)
• Silkscreen text readable (min 0.8mm height, 0.15mm line width)
• Component courtyard clearances respected (no overlaps)
• Fiducial marks present if using pick-and-place assembly
• Panel design considered if small board (add mouse bites / V-score lines)

How to Use These Checklists

When generating or reviewing a circuit:

1. Complete the Schematic Review after writing all Python circuit files.
2. Run DRC/ERC checks both in Python (structural) and in KiCad (electrical).
3. Do BOM Review after generate_bom().
4. Do Manufacturing Review after PCB layout, before generating Gerber files.

Report findings as:

• 🔴 CRITICAL: Must fix before fabrication (missing decoupling, floating pins, wrong voltage)
• 🟡 WARNING: Should fix, risk of intermittent issues (marginal thermal, no test points)
• 🟢 SUGGESTION: Nice to have, improves robustness (second-source parts, extra test points)