initial: add all custom Claude.ai skills
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---
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name: pcb-ai-engineer
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description: >
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Code-driven schematic and PCB design using Python. Primary backend: circuit-synth
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(pip install circuit-synth) with KiCad output. Covers full EE workflow: schematic
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capture as code, MCU integration (STM32, ESP32, nRF, RP2040, any MCU via extensible DB),
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power supply design, peripheral wiring, BOM generation, DRC/ERC checklists, and
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schematic review. Also supports SKiDL as alternative backend. Use this skill whenever
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the user mentions PCB design, circuit board, schematic, KiCad, Altium, EDA, hardware
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design, circuit-synth, SKiDL, component selection, BOM, DRC, ERC, power supply design,
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decoupling, voltage regulator, MCU pin assignment, or wants to describe electronics
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in Python code. Even if the user just names a chip (e.g. "STM32F407", "ESP32-S3",
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"nRF52840") in a hardware context — use this skill.
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---
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# PCB AI Engineer Skill
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Design electronics as code with Python, using circuit-synth as the primary backend
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and KiCad as the output format. Altium Designer can serve as a downstream editor
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for production-grade layouts.
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> **Cross-reference**: For firmware-level concerns (GPIO policy, watchdog strategy,
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> brown-out testing, NASA/JPL Power of Ten rules), read the `embedded-firmware-engineer`
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> skill. PCB design and firmware constraints are tightly coupled — always consider both.
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## 1. Backend Libraries
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### Primary: circuit-synth (recommended)
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```bash
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pip install circuit-synth
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# or: uv add circuit-synth
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```
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Current stable version: 0.12.x. Key features:
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- `@circuit` decorator for hierarchical subcircuit composition
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- `Component(symbol=..., ref=..., footprint=..., value=...)` with KiCad symbol library lookup
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- `Net(name)` for named electrical nets; `+=` operator for connections
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- `generate_kicad_project(output_dir)` produces `.kicad_pro`, `.kicad_sch`, `.kicad_pcb`
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- `generate_bom()` for bill of materials export
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- Bidirectional KiCad sync (Python ↔ KiCad, KiCad remains source of truth)
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- JLCPCB / DigiKey component search integration
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- FMEA analysis built-in
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API pattern (current, v0.12+):
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```python
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from circuit_synth import circuit, Component, Net
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@circuit(name="my_subcircuit")
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def my_subcircuit():
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vcc = Net("VCC_3V3")
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gnd = Net("GND")
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mcu = Component(
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symbol="RF_Module:ESP32-S3-MINI-1",
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ref="U",
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footprint="RF_Module:ESP32-S2-MINI-1",
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)
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cap = Component(
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symbol="Device:C",
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ref="C",
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value="10uF",
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footprint="Capacitor_SMD:C_0603_1608Metric",
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)
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vcc += mcu["VDD"], cap[1]
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gnd += mcu["GND"], cap[2]
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result = my_subcircuit()
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result.generate_kicad_project("output/my_board")
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```
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### Alternative: SKiDL
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Use SKiDL when the user explicitly asks for it, or for legacy projects.
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SKiDL has stronger ERC and SPICE integration but weaker KiCad 8 schematic output.
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```python
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from skidl import Part, Net, generate_netlist
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r1 = Part("Device", "R", value="1K", footprint="Resistor_SMD:R_0805_2012Metric")
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```
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### Backend selection rule
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| Signal | Backend |
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|--------|---------|
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| User says "circuit-synth" or no preference | circuit-synth |
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| User says "SKiDL" or "skidl" | SKiDL |
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| Existing project uses one of them | Match existing |
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| User needs SPICE simulation | SKiDL |
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| User needs KiCad 8 native schematic | circuit-synth |
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## 2. Project Structure
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Recommended layout for a circuit-synth project:
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```text
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project_root/
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├── main.py # Top-level board assembly
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├── mcu.py # MCU core + pin assignment
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├── power.py # Power supply subsystem
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├── peripherals.py # UART, I2C, SPI, USB, CAN blocks
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├── connectors.py # Board-level connectors, test points
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├── sensors.py # Sensor circuits (optional)
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├── mcu_db.py # MCU database (family → package → pinmap)
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├── pyproject.toml # Project metadata, circuit-synth dependency
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├── requirements.txt # circuit-synth~=0.12
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└── out/
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└── kicad_project/ # Generated KiCad files
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```
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One file per logical subsystem. Each file exports a `@circuit`-decorated function.
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`main.py` composes them all into the final board.
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## 3. MCU Database: Generic, Extensible
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The MCU database (`mcu_db.py`) is a Python dict with the schema:
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```
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vendor → family → package → {
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description, pin_count,
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pinmap: { pin_number: {signal, roles: [...], alternate_functions: [...]} },
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capabilities: { peripheral_counts, features },
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voltage_profiles: [ {id, vcore, vio, vbat} ],
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}
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```
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This is **not** a replacement for datasheets — it is a structured summary that the
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skill uses to generate skeleton circuits. The user fills in real data for their
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specific part number.
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See `references/mcu_db_schema.md` for the full schema definition and examples
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for STM32F4, ESP32-S3, and a blank template.
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### Adding a new MCU
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1. Find the datasheet for your target MCU.
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2. Copy the blank template from `references/mcu_db_schema.md`.
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3. Fill in pin assignments from the datasheet pinout table.
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4. Add capability flags (USB, ETH, CAN, ADC count, etc.).
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5. Register voltage profiles from the "Electrical Characteristics" section.
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## 4. Design Workflow
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### Phase 1: Requirements → Architecture
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1. **Clarify requirements**: What interfaces are needed? Power budget? Form factor?
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2. **Select MCU**: Based on peripheral needs, check `mcu_db.py` or suggest additions.
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3. **Define power tree**: Input source → regulators → rails → consumers.
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4. **Sketch block diagram**: MCU, power, peripherals, connectors. (Can use Mermaid.)
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### Phase 2: Python → KiCad
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1. Create `mcu_db.py` entry (or verify existing).
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2. Write `power.py` — power supply subcircuit(s).
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3. Write `mcu.py` — MCU core with decoupling, reset, boot, clock.
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4. Write `peripherals.py` — UART, I2C, SPI, USB, CAN, ADC blocks.
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5. Write `main.py` — compose everything, call `generate_kicad_project()`.
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6. Run `python main.py` — inspect generated KiCad project.
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### Phase 3: Review & Verify
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Run the **Schematic Review Checklist** (see `references/review_checklists.md`):
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- Power integrity: decoupling on every VDD pin, bulk caps, correct voltage rails
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- Signal integrity: series resistors on high-speed lines, proper termination
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- Connectivity: no floating inputs, all GND pins connected, ESD protection
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- Mechanical: mounting holes, connector placement, keep-out zones
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Run the **BOM Review** (see `references/review_checklists.md`):
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- All components have valid footprints
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- No DNP (Do Not Place) without justification
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- Supplier availability verified (JLCPCB basic parts preferred)
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### Phase 4: KiCad → Production
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1. Open generated `.kicad_pro` in KiCad.
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2. Assign footprints (if not already set in Python).
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3. Layout PCB, run DRC in KiCad.
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4. Generate Gerber, BOM, CPL files for fabrication.
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5. (Optional) Import into Altium for advanced layout / team collaboration.
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## 5. Power Supply Design Guide
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Read `references/power_design.md` for:
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- Topology selection (LDO vs. Buck vs. Buck+LDO chain vs. Boost)
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- Input protection (TVS, fuse, reverse polarity)
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- Decoupling strategy (bulk + HF per rail, local per IC)
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- Thermal considerations
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- Reference circuits for common topologies
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## 6. Handling User Requests
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When the skill activates:
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**"Design a board for [MCU/application]"**:
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1. Clarify: which MCU family? What peripherals? Power source? Form factor?
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2. Check/create `mcu_db.py` entry.
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3. Propose module structure (which `.py` files).
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4. Generate code file by file, explain design decisions.
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5. Remind about review checklists.
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**"Add [peripheral] to existing design"**:
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1. Read existing code structure.
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2. Add peripheral block function.
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3. Wire into `main.py`.
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4. Run review checklist for the changed subsystem.
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**"Review my schematic / find problems"**:
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1. Read the Python circuit code.
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2. Walk through `references/review_checklists.md` systematically.
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3. Report findings with severity (critical / warning / suggestion).
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**"Generate BOM"**:
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1. Use `result.generate_bom()` from circuit-synth.
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2. Cross-check with JLCPCB/DigiKey availability if user requests.
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## 7. Reference Files
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In `references/` directory:
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- `mcu_db_schema.md` — MCU database schema, examples (STM32F4, ESP32-S3), blank template
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- `power_design.md` — Power supply topology guide with reference circuits
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- `review_checklists.md` — Schematic review, DRC, BOM review checklists
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In `scripts/` directory:
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- `validate_mcu_db.py` — Validates mcu_db.py structure against schema
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- `bom_check.py` — Parses BOM output, checks for missing footprints/values
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## 8. Common Pitfalls
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These mistakes appear repeatedly in AI-generated PCB designs. Be vigilant:
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- **Missing decoupling caps**: Every VDD/AVDD pin needs its own 100nF cap, placed close.
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Bulk 10µF per power rail. VDDA gets a separate ferrite bead + cap.
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- **Floating inputs**: Unused MCU inputs must be tied high/low or configured as output.
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Boot/mode pins especially — always have explicit pull-up/down.
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- **USB without ESD**: Always add ESD protection diodes on USB D+/D- lines.
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- **I2C without pull-ups**: External pull-ups are mandatory; internal pull-ups are too weak
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for most applications. 4.7kΩ to VCC is the safe default.
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- **Wrong crystal load caps**: Calculate from crystal datasheet; don't guess 22pF.
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- **Power sequencing**: Multi-rail designs may require sequencing (e.g., 1.8V core before 3.3V I/O).
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- **Thermal pad not connected**: QFN/DFN exposed pads must connect to GND with thermal vias.
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ESP32 modules (MINI-1, WROOM) also have an exposed GND pad on the bottom.
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- **USB-C missing CC pull-downs**: USB-C device mode requires 5.1kΩ pull-downs on CC1/CC2.
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Without them, a USB-C host will not provide VBUS power.
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- **ESP32 strapping pins**: IO0, IO3, IO45, IO46 have boot-mode significance on ESP32-S3.
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Do not connect peripherals to strapping pins without understanding boot implications.
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- **STM32 VCAP pin missing cap**: STM32F4/F7/H7 have VCAP pins for the internal voltage
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regulator. Each needs a 2.2µF (or 4.7µF) ceramic to GND per datasheet.
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- **LDO output cap too small**: AMS1117 requires minimum 22µF low-ESR on output.
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Generic LDOs vary — always check the regulator datasheet for minimum Cout and ESR range.
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- **SPI CS# floating at boot**: Add pull-ups (10kΩ) on all SPI chip-select lines to prevent
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unintended device selection during MCU reset/boot.
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---
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# MCU Database Schema Reference
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## Schema Definition
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```python
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MCU_DB: dict[str, dict[str, dict]] = {
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"<vendor>": {
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"<family_id>": {
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"description": str, # Human-readable family description
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"core": str, # CPU core (e.g. "Cortex-M4F", "Xtensa LX7")
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"voltage_profiles": [
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{
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"id": str, # e.g. "3v3_only", "1v8_core_3v3_io"
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"vcore": float, # Core supply voltage
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"vio": float, # I/O supply voltage
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"vbat_supported": bool,
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},
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],
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"packages": {
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"<package_id>": {
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"description": str, # e.g. "LQFP64, 10x10mm, 0.5mm pitch"
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"pin_count": int,
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"thermal_pad": bool, # QFN/DFN exposed pad
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"pinmap": {
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# int pin_number or str pin_name → pin definition
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1: {
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"signal": str, # Primary signal name
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"roles": list[str], # ["power", "ground", "reset", "boot", "gpio", "analog"]
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"af": list[str], # Alternate functions (optional)
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},
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},
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"capabilities": {
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"has_usb_fs": bool,
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"has_usb_hs": bool,
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"has_eth_mac": bool,
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"has_can": bool,
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"has_sdio": bool,
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"uart_count": int,
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"i2c_count": int,
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"spi_count": int,
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"adc_channels": int,
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"dac_channels": int,
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"timer_count": int,
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"dma_channels": int,
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# extensible — add any capability flags needed
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},
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},
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},
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},
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},
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}
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```
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## Key Design Decisions
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- **Vendor as top-level key**: Allows unambiguous lookup when family names overlap.
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- **Roles list, not single role**: A pin can be both "gpio" and "analog" (e.g. PA0 on STM32).
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- **Alternate functions (af)**: Matches STM32 AF model; for ESP32, use GPIO matrix mapping.
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- **thermal_pad flag**: Reminds the generator to add GND connection for QFN/DFN pads.
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- **Capabilities are flat**: Easier to query than nested structures. Add custom keys freely.
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## Example: ST / STM32F4 / LQFP64
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```python
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MCU_DB = {
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"ST": {
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"STM32F4": {
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"description": "High-performance Cortex-M4F, up to 180 MHz, FPU, DSP",
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"core": "Cortex-M4F",
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"voltage_profiles": [
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{"id": "3v3_only", "vcore": 3.3, "vio": 3.3, "vbat_supported": True},
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{"id": "1v8_core_3v3_io", "vcore": 1.8, "vio": 3.3, "vbat_supported": True},
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],
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"packages": {
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"LQFP64": {
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"description": "LQFP64, 10x10mm, 0.5mm pitch",
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"pin_count": 64,
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"thermal_pad": False,
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"pinmap": {
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1: {"signal": "VBAT", "roles": ["power"]},
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2: {"signal": "PC13", "roles": ["gpio"], "af": ["RTC_AF1"]},
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7: {"signal": "NRST", "roles": ["reset"]},
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60: {"signal": "BOOT0", "roles": ["boot"]},
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14: {"signal": "PA0", "roles": ["gpio", "analog"],
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"af": ["ADC1_IN0", "TIM2_CH1", "USART2_CTS"]},
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15: {"signal": "PA1", "roles": ["gpio", "analog"],
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"af": ["ADC1_IN1", "TIM2_CH2", "USART2_RTS"]},
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16: {"signal": "PA2", "roles": ["gpio", "analog"],
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"af": ["ADC1_IN2", "TIM2_CH3", "USART2_TX"]},
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17: {"signal": "PA3", "roles": ["gpio", "analog"],
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"af": ["ADC1_IN3", "TIM2_CH4", "USART2_RX"]},
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# ... fill from datasheet DS9716 Table 8
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19: {"signal": "VSS", "roles": ["ground"]},
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20: {"signal": "VDD", "roles": ["power"]},
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},
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"capabilities": {
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"has_usb_fs": True,
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"has_usb_hs": False,
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"has_eth_mac": False,
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"has_can": True,
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"has_sdio": True,
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"uart_count": 4,
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"i2c_count": 3,
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"spi_count": 3,
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"adc_channels": 16,
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"dac_channels": 2,
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"timer_count": 14,
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"dma_channels": 16,
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},
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},
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},
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},
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},
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"Espressif": {
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"ESP32-S3": {
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"description": "Dual-core Xtensa LX7, WiFi + BLE 5, AI acceleration",
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"core": "Xtensa LX7 (dual)",
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"voltage_profiles": [
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{"id": "3v3_only", "vcore": 3.3, "vio": 3.3, "vbat_supported": False},
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],
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"packages": {
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"ESP32-S3-MINI-1": {
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"description": "Module, 15.4x20.5mm, castellated pads",
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"pin_count": 55,
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"thermal_pad": True,
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"pinmap": {
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1: {"signal": "GND", "roles": ["ground"]},
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2: {"signal": "3V3", "roles": ["power"]},
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3: {"signal": "EN", "roles": ["reset"]},
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4: {"signal": "IO4", "roles": ["gpio", "analog"],
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"af": ["ADC1_CH3", "TOUCH4"]},
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5: {"signal": "IO5", "roles": ["gpio", "analog"],
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"af": ["ADC1_CH4", "TOUCH5"]},
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6: {"signal": "IO6", "roles": ["gpio", "analog"],
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"af": ["ADC1_CH5", "TOUCH6"]},
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7: {"signal": "IO7", "roles": ["gpio", "analog"],
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"af": ["ADC1_CH6", "TOUCH7"]},
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# ESP32 uses GPIO matrix — any GPIO can map to any peripheral
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# af list shows default/recommended assignments
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# ... fill from ESP32-S3-MINI-1 datasheet
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},
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"capabilities": {
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"has_usb_fs": True, # USB-OTG
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"has_usb_hs": False,
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"has_eth_mac": False,
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"has_can": True, # TWAI (CAN 2.0)
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"has_sdio": True,
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"has_wifi": True,
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"has_ble": True,
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"uart_count": 3,
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"i2c_count": 2,
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"spi_count": 3, # SPI0/SPI1 for flash; SPI2/SPI3 general
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"adc_channels": 20,
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"dac_channels": 0, # S3 has no DAC (S2 did)
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"timer_count": 4, # General-purpose timers
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"dma_channels": 5, # GDMA channels
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"gpio_matrix": True, # Any GPIO → any peripheral
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
}
|
||||
```
|
||||
|
||||
## Blank Template
|
||||
|
||||
Copy this to add a new MCU family:
|
||||
|
||||
```python
|
||||
"<Vendor>": {
|
||||
"<FAMILY>": {
|
||||
"description": "",
|
||||
"core": "",
|
||||
"voltage_profiles": [
|
||||
{"id": "3v3_only", "vcore": 3.3, "vio": 3.3, "vbat_supported": False},
|
||||
],
|
||||
"packages": {
|
||||
"<PACKAGE_ID>": {
|
||||
"description": "",
|
||||
"pin_count": 0,
|
||||
"thermal_pad": False,
|
||||
"pinmap": {
|
||||
# Fill from datasheet pinout table
|
||||
},
|
||||
"capabilities": {
|
||||
"has_usb_fs": False,
|
||||
"has_usb_hs": False,
|
||||
"has_eth_mac": False,
|
||||
"has_can": False,
|
||||
"has_sdio": False,
|
||||
"uart_count": 0,
|
||||
"i2c_count": 0,
|
||||
"spi_count": 0,
|
||||
"adc_channels": 0,
|
||||
"dac_channels": 0,
|
||||
"timer_count": 0,
|
||||
"dma_channels": 0,
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
```
|
||||
|
||||
## Validation
|
||||
|
||||
Run `scripts/validate_mcu_db.py` to check:
|
||||
- All required keys present
|
||||
- Pin numbers are unique within a package
|
||||
- Every package has at least one "power" and one "ground" pin
|
||||
- Capability counts are non-negative integers
|
||||
- Voltage profiles have valid voltage ranges (0.5V–5.5V)
|
||||
@@ -0,0 +1,150 @@
|
||||
# Power Supply Design Guide
|
||||
|
||||
## Topology Selection
|
||||
|
||||
| Topology | When to Use | Efficiency | Noise | Cost |
|
||||
|----------|-------------|------------|-------|------|
|
||||
| **LDO** | Vdrop < 1V, Iout < 500mA, noise-sensitive | Low (η ≈ Vout/Vin) | Very low | Low |
|
||||
| **Buck** | Vdrop > 1V, Iout > 200mA, efficiency matters | High (85-95%) | Medium | Medium |
|
||||
| **Buck + LDO chain** | High Vin, multiple rails, mixed noise needs | Good overall | Low on LDO rails | Medium |
|
||||
| **Boost** | Vout > Vin (battery → 5V, etc.) | Medium (80-90%) | Medium-High | Medium |
|
||||
| **Buck-Boost** | Vin can be above or below Vout | Medium | High | High |
|
||||
| **Charge Pump** | Small current (<100mA), voltage doubling/inversion | Medium | High | Low |
|
||||
|
||||
### Decision Tree
|
||||
|
||||
```
|
||||
Is Vin always > Vout?
|
||||
├─ Yes → Is (Vin - Vout) < 1V AND Iout < 500mA?
|
||||
│ ├─ Yes → LDO
|
||||
│ └─ No → Is noise critical on this rail?
|
||||
│ ├─ Yes → Buck + LDO (buck for bulk, LDO for clean rail)
|
||||
│ └─ No → Buck
|
||||
└─ No → Is Vin sometimes < Vout?
|
||||
├─ Yes → Buck-Boost (or SEPIC)
|
||||
└─ No → Boost
|
||||
```
|
||||
|
||||
## Input Protection
|
||||
|
||||
Every power input should have:
|
||||
|
||||
1. **Reverse polarity protection**: P-MOSFET (preferred) or Schottky diode (simpler, lossy)
|
||||
2. **Overvoltage / transient protection**: TVS diode rated above max operating voltage
|
||||
3. **Inrush current limiting**: NTC thermistor or soft-start IC for high-capacitance designs
|
||||
4. **Fuse**: Resettable PTC or standard fuse, rated for max expected current × 1.5
|
||||
|
||||
```python
|
||||
# circuit-synth pattern: input protection block
|
||||
@circuit(name="input_protection")
|
||||
def input_protection(vin_raw, vin_protected, gnd):
|
||||
fuse = Component(symbol="Device:Fuse_Small", ref="F", value="2A",
|
||||
footprint="Fuse:Fuse_1206_3216Metric")
|
||||
tvs = Component(symbol="Diode:TVS", ref="D_TVS", value="SMBJ15A",
|
||||
footprint="Diode_SMD:D_SMA")
|
||||
cin = Component(symbol="Device:C", ref="C_IN", value="10uF",
|
||||
footprint="Capacitor_SMD:C_1206_3216Metric")
|
||||
|
||||
vin_raw += fuse[1]
|
||||
fuse[2] += tvs["A"] # TVS anode to fused input
|
||||
tvs["K"] += gnd # TVS cathode to ground (unidirectional)
|
||||
vin_protected += fuse[2], cin[1]
|
||||
gnd += cin[2]
|
||||
```
|
||||
|
||||
## Decoupling Strategy
|
||||
|
||||
### Per-IC decoupling (mandatory)
|
||||
|
||||
- **100nF ceramic (X7R/X5R, 0402 or 0603)** on every VDD pin, placed as close as possible.
|
||||
- For MCUs with VDDA (analog supply): separate 100nF + 1µF, with ferrite bead isolation.
|
||||
- For MCUs with VCAP (internal regulator output): capacitor per datasheet (typically 2.2µF).
|
||||
|
||||
### Per-rail bulk capacitors
|
||||
|
||||
- **10µF ceramic** per power rail (at the regulator output).
|
||||
- **100µF electrolytic/tantalum** for high-current rails (>500mA).
|
||||
|
||||
### High-frequency bypass
|
||||
|
||||
- **100nF + 10nF** pair for noise-sensitive analog circuits.
|
||||
- Place smaller cap closest to IC pin.
|
||||
|
||||
### Layout rules
|
||||
|
||||
- Capacitor → IC pin via is shorter than capacitor → pour via.
|
||||
- Ground vias under decoupling caps (direct path to ground plane).
|
||||
- Never route high-speed signals under/near switching regulators.
|
||||
|
||||
## Common Regulator Reference Circuits
|
||||
|
||||
### LDO: AMS1117-3.3 (SOT-223)
|
||||
|
||||
```python
|
||||
@circuit(name="ldo_3v3")
|
||||
def ldo_3v3(vin, vout_3v3, gnd):
|
||||
reg = Component(symbol="Regulator_Linear:AMS1117-3.3", ref="U_LDO",
|
||||
footprint="Package_TO_SOT_SMD:SOT-223-3_TabPin2")
|
||||
cin = Component(symbol="Device:C", ref="C_LDO_IN", value="10uF",
|
||||
footprint="Capacitor_SMD:C_0805_2012Metric")
|
||||
cout = Component(symbol="Device:C", ref="C_LDO_OUT", value="22uF",
|
||||
footprint="Capacitor_SMD:C_0805_2012Metric")
|
||||
|
||||
vin += reg["VI"], cin[1]
|
||||
vout_3v3 += reg["VO"], cout[1]
|
||||
gnd += reg["GND"], cin[2], cout[2]
|
||||
```
|
||||
|
||||
### Buck: TPS54331 (SOIC-8) — 3A, 3.5-28V input
|
||||
|
||||
```python
|
||||
@circuit(name="buck_5v")
|
||||
def buck_5v(vin, vout_5v, gnd):
|
||||
buck = Component(symbol="Regulator_Switching:TPS54331", ref="U_BUCK",
|
||||
footprint="Package_SO:SOIC-8_3.9x4.9mm_P1.27mm")
|
||||
inductor = Component(symbol="Device:L", ref="L_BUCK", value="15uH",
|
||||
footprint="Inductor_SMD:L_1210_3225Metric")
|
||||
diode = Component(symbol="Diode:SS34", ref="D_BUCK",
|
||||
footprint="Diode_SMD:D_SMA")
|
||||
# Feedback resistors, bootstrap cap, input/output caps...
|
||||
# (Complete circuit depends on exact target voltage)
|
||||
|
||||
vin += buck["VIN"]
|
||||
buck["GND"] += gnd
|
||||
buck["PH"] += inductor[1], diode["K"]
|
||||
inductor[2] += vout_5v
|
||||
diode["A"] += gnd
|
||||
```
|
||||
|
||||
## Multi-Rail Design Patterns
|
||||
|
||||
### Pattern: 12V → 5V (Buck) → 3.3V (LDO) → 1.8V (LDO)
|
||||
|
||||
Good for: general-purpose MCU boards, moderate current.
|
||||
|
||||
```
|
||||
VIN_12V ──→ [Buck] ──→ 5V rail (1A)
|
||||
├──→ [LDO] ──→ 3.3V rail (500mA)
|
||||
│ └──→ MCU VDD, peripherals
|
||||
└──→ [LDO] ──→ 1.8V rail (200mA)
|
||||
└──→ MCU VCORE (if separate)
|
||||
```
|
||||
|
||||
### Pattern: USB 5V → 3.3V (LDO)
|
||||
|
||||
Good for: simple USB-powered devices.
|
||||
|
||||
```
|
||||
USB_VBUS ──→ [Fuse 500mA] ──→ [LDO] ──→ 3.3V
|
||||
```
|
||||
|
||||
### Pattern: Battery (3.0-4.2V) → 3.3V (Buck-Boost or LDO)
|
||||
|
||||
Good for: battery-powered IoT. LDO if battery always > 3.5V; buck-boost otherwise.
|
||||
|
||||
## Thermal Considerations
|
||||
|
||||
- Calculate power dissipation: `P = (Vin - Vout) × Iout` for LDO
|
||||
- Check junction temperature: `Tj = Ta + P × θja`
|
||||
- SOT-223 θja ≈ 65°C/W; SOIC-8 ≈ 125°C/W; QFN exposed pad ≈ 35°C/W
|
||||
- If Tj > 125°C at max load → need larger package or switch to buck
|
||||
@@ -0,0 +1,115 @@
|
||||
# Review Checklists
|
||||
|
||||
## 1. Schematic Review Checklist
|
||||
|
||||
Walk through every item. Mark each as PASS / FAIL / N/A.
|
||||
|
||||
### Power
|
||||
|
||||
- [ ] Every VDD/AVDD/VDDIO pin has a dedicated 100nF decoupling cap (placed close)
|
||||
- [ ] Bulk capacitor (10µF+) present on each power rail at regulator output
|
||||
- [ ] VDDA isolated with ferrite bead + dedicated caps (if MCU has analog supply)
|
||||
- [ ] VCAP pin has capacitor per datasheet value (STM32 specific)
|
||||
- [ ] All GND pins connected (including exposed thermal pad on QFN/DFN)
|
||||
- [ ] Power sequencing considered for multi-rail designs
|
||||
- [ ] Regulator input/output caps meet datasheet ESR requirements
|
||||
- [ ] Input protection present (TVS, fuse, reverse polarity) if external power
|
||||
- [ ] USB VBUS has resettable fuse (500mA for device, per USB spec)
|
||||
- [ ] Battery circuit has undervoltage lockout if applicable
|
||||
|
||||
### Reset & Boot
|
||||
|
||||
- [ ] NRST has 100nF cap to GND (RC filter for noise rejection)
|
||||
- [ ] NRST has external pull-up (10kΩ typical) if not using reset IC
|
||||
- [ ] BOOT0 pin pulled to defined state (typically GND via 10kΩ)
|
||||
- [ ] BOOT1/other boot config pins at correct state for normal operation
|
||||
- [ ] ESP32 EN pin: 10kΩ pull-up + 1µF cap (slow rise for reliable boot)
|
||||
- [ ] ESP32 GPIO0: pull-up for normal boot, button to GND for programming
|
||||
|
||||
### Clock
|
||||
|
||||
- [ ] Crystal load capacitors calculated from datasheet formula:
|
||||
`CL = (C1 × C2) / (C1 + C2) + Cstray`, where Cstray ≈ 3-5pF
|
||||
- [ ] Crystal placed close to MCU oscillator pins (< 10mm trace length)
|
||||
- [ ] Ground guard ring / pour around crystal area (EMI reduction)
|
||||
- [ ] 32.768 kHz RTC crystal present if RTC needed (with its own load caps)
|
||||
|
||||
### Signal Integrity
|
||||
|
||||
- [ ] USB D+/D- have ESD protection diodes (TPD2E001, PRTR5V0U2X, or similar)
|
||||
- [ ] USB D+/D- traces are 90Ω differential impedance (controlled, matched length)
|
||||
- [ ] I2C bus has external pull-up resistors (4.7kΩ default; 2.2kΩ for fast-mode+)
|
||||
- [ ] SPI chip-select lines have pull-ups (prevent floating during boot)
|
||||
- [ ] UART TX/RX: series resistor (22-100Ω) if crossing board boundaries
|
||||
- [ ] High-speed signals (>10 MHz) have series termination resistors
|
||||
- [ ] CAN bus: 120Ω termination resistor at each end of bus
|
||||
- [ ] Analog inputs: RC low-pass filter if reading noisy signals
|
||||
|
||||
### GPIO & Unused Pins
|
||||
|
||||
- [ ] No floating input pins (all unused GPIO tied high/low or set as output)
|
||||
- [ ] LED current-limiting resistors present and correctly calculated
|
||||
- [ ] Button/switch inputs have debounce circuit (RC or software)
|
||||
- [ ] Test points on critical signals (power rails, I2C, SPI, UART)
|
||||
|
||||
### Connectors
|
||||
|
||||
- [ ] Programming/debug header present (SWD for ARM, JTAG if needed)
|
||||
- [ ] USB connector shield connected to GND (directly or via 1MΩ + 4.7nF)
|
||||
- [ ] All connector pins assigned and documented
|
||||
- [ ] Mechanical mounting holes present (M3 at corners, connected to GND or float)
|
||||
|
||||
## 2. DRC/ERC Checklist (pre-KiCad)
|
||||
|
||||
These should be verified in the Python code before generating KiCad files:
|
||||
|
||||
- [ ] Every `Component` has `symbol`, `ref`, and `footprint` defined
|
||||
- [ ] No duplicate reference designators (R1, R1 conflict)
|
||||
- [ ] Every net has at least two connections (no dangling nets)
|
||||
- [ ] Power nets (VCC, GND) are explicitly named and consistent
|
||||
- [ ] No unconnected component pins that should be connected
|
||||
- [ ] Component values are specified where needed (resistors, capacitors)
|
||||
|
||||
Post-KiCad-generation (in KiCad ERC):
|
||||
|
||||
- [ ] Run ERC in KiCad schematic editor — zero errors
|
||||
- [ ] Run DRC in KiCad PCB editor — zero errors
|
||||
- [ ] Check for unconnected pads in PCB
|
||||
- [ ] Verify copper pour connectivity (GND plane continuous)
|
||||
|
||||
## 3. BOM Review Checklist
|
||||
|
||||
- [ ] All components have manufacturer part number (MPN) or generic value
|
||||
- [ ] All components have valid KiCad footprint assigned
|
||||
- [ ] No DNP (Do Not Place) components without documented reason
|
||||
- [ ] Passive component values are standard E-series (E12/E24/E96)
|
||||
- [ ] Capacitor dielectric specified (X7R/X5R for decoupling, C0G for precision)
|
||||
- [ ] Capacitor voltage rating ≥ 2× operating voltage (derating)
|
||||
- [ ] Resistor power rating adequate for application
|
||||
- [ ] Check JLCPCB basic parts availability (cost optimization)
|
||||
- [ ] Second-source alternatives identified for critical components
|
||||
- [ ] Total unique part count minimized (fewer unique values = cheaper assembly)
|
||||
|
||||
## 4. Manufacturing Review (pre-Gerber)
|
||||
|
||||
- [ ] Board outline defined with correct dimensions
|
||||
- [ ] Minimum trace width / spacing meets fab capability (typically 0.15mm/0.15mm)
|
||||
- [ ] Via size meets fab capability (typically 0.3mm drill, 0.6mm annular ring)
|
||||
- [ ] Silkscreen text readable (min 0.8mm height, 0.15mm line width)
|
||||
- [ ] Component courtyard clearances respected (no overlaps)
|
||||
- [ ] Fiducial marks present if using pick-and-place assembly
|
||||
- [ ] Panel design considered if small board (add mouse bites / V-score lines)
|
||||
|
||||
## How to Use These Checklists
|
||||
|
||||
When generating or reviewing a circuit:
|
||||
|
||||
1. Complete the **Schematic Review** after writing all Python circuit files.
|
||||
2. Run **DRC/ERC** checks both in Python (structural) and in KiCad (electrical).
|
||||
3. Do **BOM Review** after `generate_bom()`.
|
||||
4. Do **Manufacturing Review** after PCB layout, before generating Gerber files.
|
||||
|
||||
Report findings as:
|
||||
- 🔴 **CRITICAL**: Must fix before fabrication (missing decoupling, floating pins, wrong voltage)
|
||||
- 🟡 **WARNING**: Should fix, risk of intermittent issues (marginal thermal, no test points)
|
||||
- 🟢 **SUGGESTION**: Nice to have, improves robustness (second-source parts, extra test points)
|
||||
@@ -0,0 +1,134 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Check BOM output for common issues.
|
||||
|
||||
Usage:
|
||||
python bom_check.py path/to/bom.csv
|
||||
|
||||
Checks:
|
||||
- All components have footprint assigned
|
||||
- All components have value assigned (resistors, capacitors, inductors)
|
||||
- No duplicate reference designators
|
||||
- Passive values are standard E-series (basic check)
|
||||
- Flags DNP components
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import csv
|
||||
import re
|
||||
import sys
|
||||
from pathlib import Path
|
||||
|
||||
# Standard E12 values (covers most common passives)
|
||||
E12_VALUES = {1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2}
|
||||
|
||||
PASSIVE_PREFIXES = {"R", "C", "L"}
|
||||
|
||||
|
||||
def normalize_value(value_str: str) -> float | None:
|
||||
"""Try to extract numeric value from component value string."""
|
||||
match = re.match(r"^(\d+\.?\d*)\s*([kKmMuUnNpP]?)", value_str.strip())
|
||||
if not match:
|
||||
return None
|
||||
|
||||
num = float(match.group(1))
|
||||
suffix = match.group(2).lower()
|
||||
|
||||
multipliers = {"k": 1e3, "m": 1e6, "u": 1e-6, "n": 1e-9, "p": 1e-12}
|
||||
return num * multipliers.get(suffix, 1.0)
|
||||
|
||||
|
||||
def is_e12_compatible(value: float) -> bool:
|
||||
"""Check if a value falls on an E12 series value (within 5% tolerance)."""
|
||||
if value <= 0:
|
||||
return False
|
||||
|
||||
# Normalize to 1.0-9.99 range
|
||||
normalized = value
|
||||
while normalized >= 10:
|
||||
normalized /= 10
|
||||
while normalized < 1:
|
||||
normalized *= 10
|
||||
|
||||
for e12 in E12_VALUES:
|
||||
if abs(normalized - e12) / e12 < 0.05:
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
def check_bom(filepath: Path) -> tuple[list[str], list[str]]:
|
||||
errors: list[str] = []
|
||||
warnings: list[str] = []
|
||||
refs_seen: set[str] = set()
|
||||
|
||||
with filepath.open(newline="", encoding="utf-8") as f:
|
||||
reader = csv.DictReader(f)
|
||||
|
||||
if reader.fieldnames is None:
|
||||
errors.append("BOM file has no headers")
|
||||
return errors, warnings
|
||||
|
||||
# Try common column name patterns
|
||||
ref_col = next((c for c in reader.fieldnames if c.lower() in ("ref", "reference", "designator")), None)
|
||||
val_col = next((c for c in reader.fieldnames if c.lower() in ("value", "val")), None)
|
||||
fp_col = next((c for c in reader.fieldnames if c.lower() in ("footprint", "package", "fp")), None)
|
||||
|
||||
if ref_col is None:
|
||||
errors.append("Cannot find reference designator column in BOM")
|
||||
return errors, warnings
|
||||
|
||||
for row_num, row in enumerate(reader, start=2):
|
||||
ref = row.get(ref_col, "").strip()
|
||||
if not ref:
|
||||
continue
|
||||
|
||||
# Duplicate check
|
||||
if ref in refs_seen:
|
||||
errors.append(f"Row {row_num}: duplicate reference '{ref}'")
|
||||
refs_seen.add(ref)
|
||||
|
||||
# Footprint check
|
||||
footprint = row.get(fp_col, "").strip() if fp_col else ""
|
||||
if not footprint:
|
||||
errors.append(f"{ref}: missing footprint")
|
||||
|
||||
# Value check for passives
|
||||
value = row.get(val_col, "").strip() if val_col else ""
|
||||
prefix = re.match(r"^[A-Z]+", ref)
|
||||
if prefix and prefix.group() in PASSIVE_PREFIXES:
|
||||
if not value or value.upper() == "DNP":
|
||||
if value.upper() == "DNP":
|
||||
warnings.append(f"{ref}: marked as DNP — verify this is intentional")
|
||||
else:
|
||||
errors.append(f"{ref}: passive component missing value")
|
||||
else:
|
||||
numeric = normalize_value(value)
|
||||
if numeric and not is_e12_compatible(numeric):
|
||||
warnings.append(f"{ref}: value '{value}' may not be standard E12 series")
|
||||
|
||||
return errors, warnings
|
||||
|
||||
|
||||
def main() -> int:
|
||||
if len(sys.argv) < 2:
|
||||
print(f"Usage: {sys.argv[0]} <path/to/bom.csv>")
|
||||
return 1
|
||||
|
||||
path = Path(sys.argv[1])
|
||||
if not path.exists():
|
||||
print(f"File not found: {path}")
|
||||
return 1
|
||||
|
||||
errors, warnings = check_bom(path)
|
||||
|
||||
for w in warnings:
|
||||
print(f" WARN: {w}")
|
||||
for e in errors:
|
||||
print(f" ERROR: {e}")
|
||||
|
||||
print(f"\n {len(errors)} errors, {len(warnings)} warnings")
|
||||
return 1 if errors else 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main())
|
||||
@@ -0,0 +1,180 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Validate MCU database structure against the expected schema.
|
||||
|
||||
Usage:
|
||||
python validate_mcu_db.py path/to/mcu_db.py
|
||||
|
||||
Checks:
|
||||
- All required keys present at each level
|
||||
- Pin numbers unique within each package
|
||||
- Every package has at least one power and one ground pin
|
||||
- Capability counts are non-negative integers
|
||||
- Voltage profiles within valid ranges
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import importlib.util
|
||||
import sys
|
||||
from pathlib import Path
|
||||
from typing import Any
|
||||
|
||||
REQUIRED_PACKAGE_KEYS = {"description", "pin_count", "pinmap", "capabilities"}
|
||||
REQUIRED_CAPABILITY_KEYS = {"uart_count", "i2c_count", "spi_count"}
|
||||
VALID_ROLES = {"power", "ground", "reset", "boot", "gpio", "analog", "nc"}
|
||||
VOLTAGE_MIN = 0.5
|
||||
VOLTAGE_MAX = 5.5
|
||||
|
||||
|
||||
def load_mcu_db(path: Path) -> dict[str, Any]:
|
||||
"""Dynamically import mcu_db.py and return MCU_DB dict."""
|
||||
spec = importlib.util.spec_from_file_location("mcu_db", path)
|
||||
if spec is None or spec.loader is None:
|
||||
raise FileNotFoundError(f"Cannot load module from {path}")
|
||||
module = importlib.util.module_from_spec(spec)
|
||||
spec.loader.exec_module(module) # type: ignore[union-attr]
|
||||
|
||||
db = getattr(module, "MCU_DB", None)
|
||||
if db is None:
|
||||
raise ValueError(f"MCU_DB not found in {path}")
|
||||
return db
|
||||
|
||||
|
||||
def validate_voltage_profile(profile: dict, path_prefix: str, errors: list[str]) -> None:
|
||||
for field in ("id", "vcore", "vio"):
|
||||
if field not in profile:
|
||||
errors.append(f"{path_prefix}: missing required field '{field}'")
|
||||
|
||||
for vfield in ("vcore", "vio"):
|
||||
v = profile.get(vfield)
|
||||
if isinstance(v, (int, float)) and not (VOLTAGE_MIN <= v <= VOLTAGE_MAX):
|
||||
errors.append(f"{path_prefix}.{vfield}={v} outside valid range [{VOLTAGE_MIN}, {VOLTAGE_MAX}]")
|
||||
|
||||
|
||||
def validate_pinmap(pinmap: dict, path_prefix: str, errors: list[str], warnings: list[str]) -> None:
|
||||
has_power = False
|
||||
has_ground = False
|
||||
seen_pins: set[Any] = set()
|
||||
|
||||
for pin_num, pin_def in pinmap.items():
|
||||
if pin_num in seen_pins:
|
||||
errors.append(f"{path_prefix}: duplicate pin number {pin_num}")
|
||||
seen_pins.add(pin_num)
|
||||
|
||||
if "signal" not in pin_def:
|
||||
errors.append(f"{path_prefix}.pin[{pin_num}]: missing 'signal'")
|
||||
|
||||
roles = pin_def.get("roles", [])
|
||||
if not roles:
|
||||
warnings.append(f"{path_prefix}.pin[{pin_num}] ({pin_def.get('signal', '?')}): no roles defined")
|
||||
|
||||
for role in roles:
|
||||
if role not in VALID_ROLES:
|
||||
warnings.append(f"{path_prefix}.pin[{pin_num}]: unknown role '{role}'")
|
||||
|
||||
if "power" in roles:
|
||||
has_power = True
|
||||
if "ground" in roles:
|
||||
has_ground = True
|
||||
|
||||
if not has_power:
|
||||
errors.append(f"{path_prefix}: no pin with role 'power' found")
|
||||
if not has_ground:
|
||||
errors.append(f"{path_prefix}: no pin with role 'ground' found")
|
||||
|
||||
|
||||
def validate_capabilities(caps: dict, path_prefix: str, errors: list[str]) -> None:
|
||||
for key in REQUIRED_CAPABILITY_KEYS:
|
||||
if key not in caps:
|
||||
errors.append(f"{path_prefix}: missing required capability '{key}'")
|
||||
|
||||
for key, value in caps.items():
|
||||
if key.endswith("_count") or key.endswith("_channels"):
|
||||
if not isinstance(value, int) or value < 0:
|
||||
errors.append(f"{path_prefix}.{key}={value!r}: must be non-negative int")
|
||||
|
||||
|
||||
def validate_db(db: dict[str, Any]) -> tuple[list[str], list[str]]:
|
||||
errors: list[str] = []
|
||||
warnings: list[str] = []
|
||||
|
||||
if not isinstance(db, dict):
|
||||
errors.append("MCU_DB must be a dict")
|
||||
return errors, warnings
|
||||
|
||||
for vendor, families in db.items():
|
||||
if not isinstance(families, dict):
|
||||
errors.append(f"MCU_DB['{vendor}'] must be a dict of families")
|
||||
continue
|
||||
|
||||
for family_id, family in families.items():
|
||||
fpath = f"{vendor}/{family_id}"
|
||||
|
||||
if "description" not in family:
|
||||
warnings.append(f"{fpath}: missing 'description'")
|
||||
|
||||
for vp in family.get("voltage_profiles", []):
|
||||
validate_voltage_profile(vp, f"{fpath}/voltage_profiles", errors)
|
||||
|
||||
packages = family.get("packages", {})
|
||||
if not packages:
|
||||
errors.append(f"{fpath}: no packages defined")
|
||||
|
||||
for pkg_id, pkg in packages.items():
|
||||
ppath = f"{fpath}/{pkg_id}"
|
||||
|
||||
missing_keys = REQUIRED_PACKAGE_KEYS - set(pkg.keys())
|
||||
if missing_keys:
|
||||
errors.append(f"{ppath}: missing keys {missing_keys}")
|
||||
|
||||
pinmap = pkg.get("pinmap", {})
|
||||
if not pinmap:
|
||||
warnings.append(f"{ppath}: pinmap is empty (needs datasheet data)")
|
||||
else:
|
||||
validate_pinmap(pinmap, ppath, errors, warnings)
|
||||
|
||||
caps = pkg.get("capabilities", {})
|
||||
validate_capabilities(caps, ppath, errors)
|
||||
|
||||
return errors, warnings
|
||||
|
||||
|
||||
def main() -> int:
|
||||
if len(sys.argv) < 2:
|
||||
print(f"Usage: {sys.argv[0]} <path/to/mcu_db.py>")
|
||||
return 1
|
||||
|
||||
path = Path(sys.argv[1])
|
||||
if not path.exists():
|
||||
print(f"File not found: {path}")
|
||||
return 1
|
||||
|
||||
try:
|
||||
db = load_mcu_db(path)
|
||||
except Exception as exc:
|
||||
print(f"Failed to load MCU_DB: {exc}")
|
||||
return 1
|
||||
|
||||
errors, warnings = validate_db(db)
|
||||
|
||||
for w in warnings:
|
||||
print(f" WARN: {w}")
|
||||
for e in errors:
|
||||
print(f" ERROR: {e}")
|
||||
|
||||
total_vendors = len(db)
|
||||
total_families = sum(len(v) for v in db.values())
|
||||
total_packages = sum(
|
||||
len(f.get("packages", {}))
|
||||
for v in db.values()
|
||||
for f in v.values()
|
||||
)
|
||||
|
||||
print(f"\nSummary: {total_vendors} vendors, {total_families} families, {total_packages} packages")
|
||||
print(f" {len(errors)} errors, {len(warnings)} warnings")
|
||||
|
||||
return 1 if errors else 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main())
|
||||
Reference in New Issue
Block a user